Define something with a Makefile

[Energon]

How do I setup an external define using a Makefile? I have this in my Makefile:

DEBUG=_DEBUG
...
$(CXX) -o .... -g -D$(DEBUG)

and when I do a `make debug`, I get this:

g++ -o .... -g -D_DEBUG

which looks to me like _DEBUG should now be defined, but in my code where I have:

#if defined _DEBUG
...
#endif

the code never gets executed... what am I doing wrong? I'm trying to write some code that syncs in both Windows and Linux and I have my Debug build setup to define _DEBUG in Windows, and I want that same kind of functionality here...

[Dru Lee Parsec]

I believe that inside a bash shell script (which is essentially what a make file is) that any environment variables that get set have scope only inside that script.

So if I have a script that says:

export name=dru

Then the variable "name" is only valid inside that script.

This is more of a bash shell issue than a make file issue. Do any of the shell script gurus here know how to do this?

[Energon]

*scratches head*

umm... actually, I'm talking about using the -D parameter to g++... to define something outside of the code... it dawned on me that the problem is that I'm doing it after all my .o files are created (during the link phase)... but I don't know how to get it to happen during compilation...